(1) Field of the Invention
The present invention describes both a structure and method of fabricating copper metal-insulator-metal (MIM) capacitors and thick metal inductors simultaneously, with only one addition mask, for high frequency mixed-signal or Rf, CMOS applications, in a dual damascene trench and via process.
(2) Description of the Relate Art
As a background to the current invention, in many mixed signal or high frequency Rf applications both high performance, high speed capacitors and inductors are required. Low series resistance, low loss, high Q and low (RC) time constants are required in these high frequency applications for high performance. In addition, it is important to fabricate device structures by processes compatible with CMOS processing with AlCu alloys to pure copper in dual damascene structures.
A metal-insulator-metal (MIM) capacitor is used commonly in high performance applications in CMOS technology. Typically, the capacitor has a sandwich structure and can be described as a parallel plate capacitor. The capacitor top metal (CTM) is separated from the capacitor bottom metal (CBM) by a thin insulating layer. Both two parallel plates are conventionally made from Al or AlCu alloys. These metals are patterned and etched needing several photolithography photo masking steps. The thin insulating dielectric layer is usually made from silicon oxide or silicon nitride deposited by chemical vapor deposition (CVD).
The damascene processing is a xe2x80x9cstandardxe2x80x9d method for fabricating planar copper interconnects. Damascene wiring interconnects (and/or studs) are formed by depositing a dielectric layer on a planar surface, patterning it using photolithography and oxide reactive ion etch (RIE), then filling the recesses with conductive metal. The excess metal is removed by chemical mechanical polishing (CMP), while the troughs or channels remain filled with metal. For example, damascene wiring lines can be used to form bit lines in DRAM devices, with processing similar to the formation of W studs in the logic and DRAM devices. In both examples, sputtered Ti/TiN liners, underlying diffusion barriers, have been coated with chemical vapor deposited (CVD) W metal, then polished back to oxide.
In the dual-damascene process, a monolithic stud/wire structure is formed from the repeated patterning of a single thick oxide film followed by metal filling and CMP. First, a relatively thick oxide layer is deposited on a planar surface. The oxide thickness is slightly larger than the desired final thickness of the stud and wire, since a small amount of oxide is removed during CMP. Stud recesses are formed in the oxide using photolithography and RIE that either partially etches through the oxide or traverses the oxide and stops on the underlying metal to be contacted. The wire recesses can then be formed using a separate photolithography step and a timed oxide etching step. If the former stud RIE option is used, the wire etching completes the drilling of the stud holes.
Next, the stud/wire metallization is deposited, then planarized using CMP. The resulting interconnects are produced with fewer process steps than with conventional processing and with the dual damascene process, two layer of metal are formed as one, i.e., wiring line and contact stud vias, avoiding an interface between the layers.
Another metal deposition, besides sputtering techniques, has been adapted as a standard for copper metallization. This technique is electrochemical deposition (ECb) of copper. The electrochemical copper deposition (ECD) still needs, e.g., sputtering techniques, physical vapor deposition (PVD), to deposit thin underlying diffusion barrier film (Ta,TaN) and a conductive xe2x80x9cseedxe2x80x9d layer of copper.
Related patents and relevant literature now follow as Prior Art, summarized below.
U.S. Pat. No. 5,879,985 entitled xe2x80x9cCrown Capacitor Using a Tapered Etch of a Damascene Lower Electrodexe2x80x9d granted Mar. 9. 1999 to Gambino et al. shows a capacitor using a damascene process for the lower electrode. Upper capacitor structure has a xe2x80x9ccrownxe2x80x9d type structure.
U.S. Pat. No. 5,406,447 entitled xe2x80x9cCapacitor Used in an Integrated Circuit and Comprising Opposing Electrodes Having Barrier Metal Films in Contact with a Dielectric Filmxe2x80x9d granted Apr. 11, 1995 to Miyazaki teaches a process for a planar metal-insulator-metal (MIM) capacitor. Barrier metal films are composed of platinum,. palladium, tantalum, or titanium nitride. The capacitor dielectric material is either tantalum oxide or a perovskite oxide, such As strontium titanate or a composite of lead zirconate and lead titanate, which are ferroelectric type materials.
U.S. Pat. No. 5,208,726 entitled xe2x80x9cMetal-Insulator-Metal (MIM) Capacitor-Around-Via Structure for a Monolithic Microwave Integrated Circuit (MMIC) and Method of Manufacturing Samexe2x80x9d granted May 4, 1993 to Apel teaches a MIM capacitor structure and method for monolithic microwave IC applications. A low inductance connection is provided between a front side MIM capacitor and a backside ground plane.
U.S. Pat. No. 5,194,932 entitled xe2x80x9cSemiconductor Integrated Circuit Devicexe2x80x9d granted Mar. 16, 1993 to Kurisu teaches a metal-insulator-metal (MIM) capacitor method. The ground pattern, the insulating inter layer, and the power source pattern come together to form a MIM type capacitor.
U.S. Pat. No. 5,293,510 entitled xe2x80x9cSemiconductor Device with Ferroelectric and Method of Manufacturing the Samexe2x80x9d granted Mar. 8, 1994 to Takenaka discloses a ferroelectric capacitor process.
U.S. Pat. No. 5,675,184 entitled xe2x80x9cIntegrated Circuit Devicexe2x80x9d granted Oct. 7, 1997 to Matsubayashi et al. teaches a metal-insulator-metal (MIM) capacitor process in an Rf application. Thermoplastic material and magnetic substance layers are described.
The present invention describes a structure and method of fabricating copper metal-insulator-metal (MIM) capacitors and thick metal inductors simultaneously, using only one photolithography mask, for high frequency, mixed-signal or Rf, CMOS applications, in a dual damascene trench and via process.
The structure and process embodiments of this invention start with the first process step, the forming by damascene and chemical mechanical polishing (CMP) the first level inlaid metal structures. The process sequence is as follows: an insulating layer is deposited. This first insulating layer, e.g., silicon oxide, is patterned and reactive ion etched (RIE) upon a semiconductor substrate. The next processing step in building of the damascene structure, is the deposition by sputtering (PVD, physical vapor deposition) and patterning of a thin metal barrier layer (trench liner), e.g. Ta,TaN, and a thin copper seed layer. Copper metal is deposited upon the seed layer in the openings in insulator by electrochemical copper deposition (ECD). The excess copper metal is polished off and planarized with surface by chemical mechanical polishing (CMP) forming the first level metal for the capacitor bottom metal (CBM) layer.
Continuing with the summation of the structure and process embodiments of this invention, is the second step in this CMOS process, the deposition of a copper metal protecting xe2x80x9cbuffer layerxe2x80x9d. This layer is needed to prevent, copper corrosion with silicon oxide layers. It is deposited over the first level inlaid metal structures and first insulator layer. This buffer layer is, e.g., silicon nitride. The third process step is the blanket deposition of an intermetal dielectric (IMD) layer upon the buffer layer. This intermetal dielectric (IMD) is, e.g., silicon oxide, silicon nitride, or FSG fluoro-silicate glass, or PSG phosphosilicate glass. The fourth step is to form a photoresist masking layer by a lithography process, defining simultaneously both the metal-insulator-metal (MIM) capacitor and inductor area, over the first level of metal. Photoresist is coated and patterned upon the intermetal dielectric (IMD) layer. A reactive ion etch (RIE) is performed to etch the intermetal dielectric layer (IMD) layer, forming openings and stopping on the buffer layer. The fifth step is removal of the photoresist material and the metal protecting buffer layer in the exposed opening areas. The sixth and seventh steps are the deposition of both a insulating protecting buffer layer, i.e., silicon nitride, and an insulating layer, i.e., silicon oxide.
Another embodiment of this invention is that the insulating protecting buffer layer (described above) and the insulator layer (described above) can be combined into just one silicon nitride layer, as an alternate process step. This consolidates the processing.
Continuing with the summation of the structure and process embodiments of this invention is the eighth step, the deposition of a conducting metal buffer layer, i.e., tantalum nitride. The ninth step is the formation of a xe2x80x9cstandardxe2x80x9d dual damascene structure with contact via and interconnect trench. In addition, the metal-insulator-metal (MIM) capacitor and inductor structures are nearly completed in the following processes. The via and trench structures are produced by photoresist patterning and reactive ion etching (RIE) processes primarily in the layer of intermetal dielectric (IMD). Also etched in this part of a standard dual damascene process are the conducting metal buffer layer, insulator layer, insulating protecting buffer layer and the copper metal protecting xe2x80x9cbuffer layerxe2x80x9d.
A key process step and yet another embodiment of this invention is that the metal-insulator-metal capacitor (MIM) and inductor areas are protected during the aforementioned standard dual damascene process. The patterning photoresist is stripped exposing all open areas: trench/via area and MIM/Inductor area. Next, all the open areas in the intermetal (IMD) consisting of MIM/Inductor area, via and trench (for interconnect line) structures are filled with a conductive metal protect buffer layer, tantalum nitride.
Another key embodiment of this invention is the tenth process in this CMOS compatible process. This processing step is the processing needed to form simultaneously: both the standard dual damascene copper metals structures with contact vias, interconnect trenches and metal-insulator-metal (MIM) capacitors and, at the same time, inductors structures. The open areas in the intermetal dielectric (IMD) consists of: MIM/Inductor areas, vias and trenches (interconnect lines) structures. These open areas are filled with a conductive copper metal on top of the conductive metal protect buffer layer.
Continuing with the summation of the structure and process embodiments of this invention is the eleventh process step. This processing step is the forming simultaneously of standard dual damascene copper metals structures with contact via, interconnect trench and, at the same time, both the metal-insulator-metal (MIM) capacitor and inductor structures by damascene and chemical mechanical polishing (CMP) back the excess metal to form inlaid copper metal structures. The excess copper metal and excess conductive metal protect buffer layer are polished off and planarized with surface by chemical mechanical polishing (CMP) forming inlaid copper which remains in the open regions. An embodiment of this invention, which is both a process and structure variation, is to chem-mech polish back: both the excess copper (described above) and the excess metal protect buffer layer (described above), polishing through the excess insulator layer and stopping on the insulating protect buffer layer.
In yet another embodiment of the present invention is another process variation or process option or the eleventh step, which is to chem-mech polish back: both the excess copper and excess metal protect buffer layer, polishing through both the excess insulator layer and the excess insulating protect buffer layer, and finally stopping on the intermetal dielectric (IMD) layer. The end result is the formation, by damascene and chemical mechanical polishing (CMP), of inlaid copper metal structures (with slightly more copper metal removal than described in the previous process step): interconnect/trench, contact/via and MIM/inductor.
This invention has been summarized above and described with reference to the preferred embodiments. Some processing details have been omitted and are understood by those skilled in the art. More details of this invention are stated in the xe2x80x9cDESCRIPTION OF THE PREFERRED EMBODIMENTSxe2x80x9d section.